Noise Tolerant Circuits for Modified Feedthrough Logic

In this paper a circuit design technique to improve noise tolerant of a new CMOS domino logic family called feedthrough logic is presented. The feedthrough logic improves the performance of arithmetic circuit as compared to static CMOS and domino logic but its noise tolerant is very less. A 2-input NAND gate is designed by the proposed technique. The ANTE (average noise threshold energy) metric is used for the comparison of noise tolerance of proposed circuit with the feedthrough logic. Simulation results for a 2input NAND gate at 0.18-μm, 1.8 V CMOS process technology show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction leakage power. Keywords-Feedthrough logic (FTL); average noise threshold energy (ANTE); leakage power; sub-threshold leakage current; noise immunity curves; noise tolerant circuits.